

import chisel3._
import chisel3.util._

// class CacheBusId extends Bundle with AxiParameters {
//   val id = Output(UInt(AxiIdWidth.W))
// }

class CacheBusReq extends Bundle  with AxiParameters {
  val addr = Output(UInt(AxiAddrWidth.W))
  val ren = Output(Bool())
  val wdata = Output(UInt(AxiDataWidth.W))
  val wmask = Output(UInt((AxiDataWidth / 8).W))
  val wen = Output(Bool())
  val size = Output(UInt(2.W))  
}

class CacheBusResp extends Bundle with AxiParameters {
  val rdata = Output(UInt(AxiDataWidth.W))
}

class CacheBusIO extends MemIO {
  val req = Decoupled(new CacheBusReq)
  val resp = Flipped(Decoupled(new CacheBusResp))
}

//with CacheBusId 
